SPI - Slave 2 Configuration

Report Type: IN / OUT
Report Size: 18 Bytes
Acknowledged By: Command Acknowledgement

Report ID	Unlock Key	Baud Rate Flags	Baud Rate LSB	Baud Rate MSB	Clock Flags	Mode Flags	MISO Flags	Frame Synchronisation Flags	Frame Synchronisation Counter	Audio Flags
0001 010 I	8 bytes	u i 000000	bbbbbbbb	000 bbbbb	u i 0000 p e	u i 0000 mm	u i 0000 S s	u i 00 n w P E	00000 ppp	u i 00 N m pp

Report ID

HID Report ID. Always 0x14 for OUT Reports.

IN Reports can use the I flag to indicate whether the Host should receive the immediate values of the Master peripheral (when I is 1) or whether the Host should receive the configuration settings (when I is 0).

Unlock Key

An 8-byte key that is used to prevent accidental changes to certain configuration values. If the supplied key does not match the stored key then this report is ignored.

For IN Reports the field is set as all zeroes.

Common Flags

These flags are common across multiple fields and have the same semantics for each:

Bits	Direction	Meaning
u	OUT	Update the field; 1 if the field is to be updated, 0 if no change is to be made (any supplied values will be ignored). For IN Reports this will be set to 0.
i	OUT	Immediate update; 1 if an update is to be applied immediately, 0 if the change will be stored in the configuration to be applied later. Note that no configuration changes are persisted until Store Current Configuration is issued. This flag makes no sense if u is 0, so will be ignored. For IN Reports this will be set to 0.

Baud Rate

This field is the value given to the SPI Baud Rate Generator and directly specifies the spacing of the bits put onto the bus for the given slave. The desired value can be in the range [0, 8191] (values outside this range will be clamped) and relates to the clock frequency by the formula F_clk = F_pc / (2 * *Baud Rate* + 1). See the notes below on F_clk and F_pc.

This field is Little Endian, ie. the Least Significant Byte of the word appears first. Bit numbering within the constituent bytes is unaffected.

About Throughput

The PIC operates at a pipelined instruction rate of 24MHz so clearly a 12MHz maximum SPI clock frequency can only be used in bursts (not strictly true since DMA channels can be leveraged in an auto-restarting mode but for the purposes of this application that is not feasible). The default firmware uses DMA to transfer up to 1KiB of data to and from memory so transfers from the Host to an SPI Slave are limited to 1023 bytes. Using the USB HID protocol, 1023 bytes will take 17 frames to transfer - approximately 17ms.

Transfers from an SPI Slave to the Host can be up to 65535 bytes but the limiting factor for throughput will again be the USB HID interface which can transfer at most 64 bytes per millisecond (64kB per second) for the factory firmware, before the overhead for the report headers are taken into account. This means that for high SPI clock frequencies the data transfer will be paused when the buffer is full whilst the buffer is transferred to the Host. For Framed SPI modes the clock will continue to run; for regular SPI modes the clock will be in its idle state. In both modes the Slave Select line will not be released until the entire transaction has been completed.

Theoretically the 12MHz SPI port could transfer stereo 16-bit ADC samples at 375kHz although the PIC would not be able to process them other than to pass them to another serial port via DMA transfers. Using the USB HID interface with the default factory firmware you’re probably looking at more on the order of 16kHz stereo 16-bit ADC samples maximum, probably a few kHz less. You could achieve significantly better than this with custom firmware that processes the samples or uses a different USB protocol, or even HID and multiple endpoints.

Peripheral Clock Frequency, Fpc (MHz)

The Peripheral Clock Frequency, Fpc, is the input clock to the SPI Baud Rate Generator and is derived from the internal RC oscillator. The datasheet specifies a variation of +/- 2% over process, voltage and temperature, although when locked to the USB Frame Packets the variation can be as little as +/- 0.2%:

Min	Typ	Max
23.52	24.00	24.48

SPI Clock Frequency, Fclk (MHz)

Because each slave has its own Slave Select line the properties on the bus, such as clock rate, can be set for each of the slaves individually. The frequency of the clock line will vary with the Peripheral Clock Frequency which is nominally 24MHz. The various formulae are given in the table below:

Bus Clock Frequency, MHz	Formula
Minimum	Fpcmin / (2 * Baud Rate) + 1)
Typical	Fpctyp / (2 * Baud Rate) + 1)
Maximum	Fpcmax / (2 * Baud Rate) + 1)

Some sample Baud Rate values have been calculated for convenience:

Baud Rate	Minimum (kHz)	Typical (kHz)	Maximum CLK (kHz)
0	11760.00	12000.00	12240.00
11	980.00	1000.00	1020.00
23	490.00	500.00	510.00
119	98.00	100.00	102.00
1199	9.80	10.00	10.20
8191	1.43	1.46	1.50

Clock Flags

Bits	Direction	Meaning
p	IN / OUT	Polarity; 1 if the Idle state is high, 0 if the idle state is low.
e	IN / OUT	Edge output; 1 if MOSI changes when the clock transitions from from Active to Idle, 0 if MOSI changes when the clock transitions from Idle to Active.

Mode Flags

The Mode Flags field determines the operating mode of the SPI peripheral. It affects transfers differently depending on whether the peripheral is operating in Audio Mode (see below) or not. For regular SPI transfers Mode Flags can have the following values:

Mode (mm)	Data Width
00	8-bit transfers
01	16-bit transfers
10	32-bit transfers
11	32-bit transfers

When the SPI peripheral is in Audio Mode the bits will have the following effect:

Mode (mm)	Data Width	Channel Width	Frame Width
00	16 bits	16 bits	32 bits
01	16 bits	32 bits	64 bits
10	32 bits	32 bits	64 bits
11	24 bits	32 bits	64 bits

MISO Flags

Bits	Direction	Meaning
S	IN / OUT	Sign-extend; 1 if the MISO values are to be sign-extended, 0 if not.
s	IN / OUT	Sample point; 1 if MISO is sampled at the end of the output period, 0 if it is sampled in the middle.

Frame Synchronisation Flags

Bits	Direction	Meaning
n	IN / OUT	Enabled; 1 if the frame pulse is enabled, 0 if the frame pulse is disabled.
w	IN / OUT	Width; 1 if the frame pulse is one character wide, 0 if the frame pulse is one clock wide.
P	IN / OUT	Polarity; 1 if the frame pulse is active-high, 0 if the frame pulse is active-low.
E	IN / OUT	Edge; 1 if the frame pulse coincides with the first bit clock, 0 if the frame pulse precedes the first bit clock.

Frame Synchronisation Counter

This field is updated depending on the u and i flags of the Frame Synchronisation Flags field. It contains the number of characters between frame pulses and has one of the following values:

Bits (fff)	Meaning
000	A frame synchronisation pulse is generated for every character.
001	A frame synchronisation pulse is generated every 2 characters.
010	A frame synchronisation pulse is generated every 4 characters.
011	A frame synchronisation pulse is generated every 8 characters.
100	A frame synchronisation pulse is generated every 16 characters.
101	A frame synchronisation pulse is generated every 32 characters.
110	Invalid - will result in a Negative Command Acknowledgement response.
111	Invalid - will result in a Negative Command Acknowledgement response.

Audio Flags

Bits	Direction	Meaning
N	IN / OUT	Enabled; 1 if the audio mode is enabled, 0 if the audio mode is disabled.
m	IN / OUT	Mono; 1 if each MOSI word is transmitted on both channels, 0 if the MOSI words are stereo.
pp	IN / OUT	Protocol; 00 is I2S, 01 is left-justified, 10 is right-justified, and 11 is PCM / DSP mode.